Field of the Invention
The invention relates to an integrated semiconductor memory and to a method for fabricating a semiconductor memory of this type. The integrated semiconductor memory, in general, has memory cells in a semiconductor substrate, each memory cell having a storage capacitor, which is arranged in a trench and above which there is a trench filling having a first, thin insulation layer and a first conductive filling on the inner side of the first insulation layer in the trench. A vertical selection transistor is formed at a land formed from substrate material. Word lines, which are each separated from the land by a second, thin insulation layer, run on two opposite side walls of the land. In each case, the first insulation layer of the trench filling adjoins a further side wall of the land.
Integrated semiconductor memories have a multiplicity of memory cells on a semiconductor substrate, which each have a storage capacitor and a selection transistor for selection of these memory cells. The selection transistors are driven by word lines and bit lines. Buried storage capacitors are produced deep inside trenches which are circular or approximately oval in contour as a result of a dielectric being introduced onto the inner wall of the trench and an inner capacitor electrode being formed therein. The surrounding substrate is used as the outer capacitor electrode. At mid-substrate depth above the storage capacitors there is generally a collar region which is used to make electrical contact with the inner capacitor electrode and otherwise to provide insulation with respect to surrounding electrical structures close to the substrate surface. Above this the selection transistors are formed, often within these trenches but in an upper region.
In another design of selection transistors, the latter are located laterally next to the trenches for the storage capacitors. In a specific design—referred to as a surrounding gate transistor—the selection transistors are vertical transistors which are formed at lands, i.e. vertical columns which are, for example, square or rectangular in cross section. At the side walls, the land has a shell which runs all the way around it or at least covers two opposite side walls and comprises gate electrodes; an upper source/drain electrode is implanted in an upper region, and a lower source/drain electrode is produced in a lower region below the gate electrode by diffusion of a dopant out of the trench capacitor. A thin gate oxide layer is formed between the substrate material in the lands and the lateral gate electrodes, while the channel region of the transistor, preferably of a MOSFET (metal oxide semiconductor field effect transistor), runs in the vertical direction beneath the gate oxide layer but at both opposite or all four side walls.
A problem with forming the transistors designed in this way is the step of forming the word lines which constitute the gate electrodes. Ideally, all four side walls of the lands are covered by the gate electrode, in particular including that side wall of the land which adjoins the trench with the storage capacitor of the same memory cell, where the lower source/drain electrode is formed approximately at the level of the gate electrode lower edge and beneath the gate electrode. However, in the spacer technique, the gate electrodes are formed as side wall coverings, specifically by conformal deposition and subsequent anisotropic etchback in a direction perpendicular to the substrate surface. The material of the gate electrodes or word lines remains in place only on vertical wall of the substrate or of other structures. If the gate electrode is to be formed at all four side walls of a land, the land has to be surrounded by a trench from all four sides. In this case, the spacer technique merely leads to the individual cells being surrounded but not to them being electrically connected to one another. Consequently, the gate electrodes belonging to a row of memory cells have to be subsequently electrically connected by additional structures, i.e. with the aid of further lithographic process steps.
Alternative gate designs for transistors of the above design are described in U.S. Pat. No. 5,519,236. In one embodiment, only two opposite side walls of a land are covered with gate electrodes. No gate electrode is formed at the side wall of the land which adjoins the trench having the storage capacitor of the same memory cell and at the opposite side wall. Instead, at these side walls there is an insulating filling which extends as far as the next land flush in line with the land cross section, so that the gate electrodes can also be deposited on the side walls of these insulating land extensions. Consequently, each land has a left-hand and right-hand word line, with the result that ultimately two parallel-connected selection transistors are formed at each land. Eddy currents between the two transistors lead to switching inaccuracies when the memory cell is driven.
To avoid this disadvantageous switching behavior, it is possible for further columns, along which the right-hand and left-hand word lines likewise extend, to be formed between the adjacent lands. These additional columns, which serve as auxiliary structures, are at only a short distance from the two adjacent lands. Between them there is a gap in which the gate electrode is likewise formed. Each land made from substrate material for forming a vertical transistor is therefore covered with a gate electrode from all four sides, i.e. including toward the adjoining storage trench. Moreover, the gate electrodes are conductively connected to one another in rows along the column-like auxiliary structures, since the spacers are also formed around these structures. A drawback of this arrangement is the additional outlay on time, labor and costs required to form the auxiliary structures.